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?1 CXA3086Q 48 pin qfp (plastic) e95619c77 6-bit 140msps flash a/d converter description the CXA3086Q is an 6-bit high-speed flash a/d converter capable of digitizing analog signals at the maximum rate of 140msps. ecl, pecl or ttl can be selected as the digital input level in accordance with the application. the ttl digital output level allows 1: 2 demultiplexed output. features differential linearity error: 0.2lsb or less integral linearity error: 0.2lsb or less high-speed operation with a maximum conversion rate of 140msps low input capacitance: 7pf wide analog input bandwidth: 200mhz low power consumption: 358mw low error rate excellent temperature characteristics 1: 2 demultiplexed output 1/2 frequency divided clock output (with reset function) compatible with ecl, pecl and ttl digital input levels single +5v power supply operation available surface mounting package pin configuration (top view) structure bipolar silicon monolithic ic applications magnetic recording (prml) communications (qpsk, qam) lcds digital oscilloscopes sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. dv ee 3 v rb v rbs av cc n.c. v in av cc v rt v rts agnd dgnd3 agnd clk/e dv cc 2 clk/t dgnd2 p1d0 (lsb) p1d1 p1d2 p1d3 p1d4 p1d5 (msb) dgnd2 clkn/e dv cc 2 n.c. dgnd1 ps clkout inv select n.c. dgnd1 dv cc 1 dv cc 2 dv cc 1 dgnd2 p2d2 p2d1 p2d3 p2d4 p2d5 (msb) dgnd2 dv cc 2 resetn/t reset/e resetn/e p2d0 (lsb) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1
?2 CXA3086Q absolute maximum ratings (ta = 25?) unit supply voltage av cc , dv cc 1, dv cc 2 ?.5 to +7.0 v dgnd3 ?.5 to +7.0 v dv ee 3 ?.0 to +0.5 v dgnd3 ?dv ee 3 ?.5 to +7.0 v analog input voltage v in v rt ?2.7 to av cc v reference input voltage v rt 2.7 to av cc v v rb v in ?2.7 to av cc v |v rt ?v rb | 2.5 v digital input voltage ecl ( *** /e * 1 )dv ee 3 to +0.5 v pecl ( *** /e) ?.5 to dgnd3 v ttl ( *** /t, inv, ps) ?.5 to dv cc 1v other (select) ?.5 to dv cc 1v vid * 2 (| *** /e ? *** n/e|) 2.7 v storage temperature tstg ?5 to +150 ? allowable power dissipationp d 1.2 w (when mounted on a glass fabric base epoxy board with 76mm x 114mm, 1.6mm thick) recommended operating conditions with a single power supply with dual power supplies unit min. typ. max. min. typ. max. supply voltage dv cc 1, dv cc 2, av cc +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 v dgnd1, dgnd2, agnd ?.05 0 +0.05 ?.05 0 +0.05 v dgnd3 +4.75 +5.0 +5.25 ?.05 0 +0.05 v dv ee 3 ?.05 0 +0.05 ?.5 ?.0 ?.75 v analog input voltage v in v rb v rt v rb v rt v reference input voltage v rt +2.9 +4.1 +2.9 +4.1 v v rb +1.4 +2.6 +1.4 +2.6 v |v rt ?v rb | 1.5 2.1 1.5 2.1 v digital input voltage ecl ( *** /e) : v ih dgnd3 ?1.05 dgnd3 ?0.5 v : v il dgnd3 ?3.2 dgnd3 ?1.4 v pecl ( *** /e) : v ih dgnd3 ?1.05 dgnd3 ?0.5 v : v il dgnd3 ?3.2 dgnd3 ?1.4 v ttl ( *** /t, inv, ps): v ih 2.0 2.0 v : v il 0.8 0.8 v other (select) : v ih dv cc 1dv cc 1v : v il dgnd1 dgnd1 v vid * 2 (| *** /e ? *** n/e|) 0.4 0.8 0.4 0.8 v maximum conversion rate fc (straight mode) 100 100 msps (dmux mode) 140 140 msps ambient temperature ta ?0 +75 ?0 +75 ? * 1 *** /e and *** /t indicate clk/e and clk/t, etc. for the pin name. * 2 vid: input voltage differential ecl and pecl switching level vid v il (min.) v ih v th (dgnd3 ?1.2v) v il v ih (max.) dgnd3
?3 CXA3086Q block diagram p1d0 p2d1 p1d1 p1d2 p1d3 p1d4 p1d5 (lsb) (msb) p2d0 p2d2 p2d3 p2d4 p2d5 (lsb) (msb) 1 2 30 31 32 33 62 63 r r 1 r 6bit 6bit 6bit av cc dv cc 2 inv dgnd3 ttlout latchb ttlout latcha 6bit latch encoder 6bit delay select dq q select ps dv ee 3 dgnd2 agnd clkout n.c. dgnd1 dv cc 1 r r r v rts v rb v rbs clk/t clk/e clkn/e resetn/t resetn/e reset/e v rt v in r r r r r 2 17 20 42 9 28 37 48 30 31 32 33 34 35 7 6 5 4 3 2 18 40 45 43 13 36 29 8 1 46 39 41 44 23 14 11 12 10 26 25 27 15 16 19 21 22 24 38 47
?4 CXA3086Q pin description and i/o pin equivalent circuit analog ground. separated from the digital ground. analog power supply. separated from the digital power supply. digital ground. digital power supply. digital power supply. ground for ecl input. +5v for pecl and ttl input. digital power supply. ?v for ecl input. ground for pecl and ttl input. no connected pin. not connected with the internal circuits. clock input. clk/e complementary input. when left open, this pin goes to the threshold potential. only clk/e can be used for operation, but complementary input is recommended to attain fast and stable operation. reset input. when the input is set to low level, the built-in clk frequency divider circuit can be reset. resetn/e complementary input. when left open, this pin goes to the threshold voltage. only resetn/e can be used for operation. 14, 23 17, 20 1, 8, 29, 36, 39, 46 9, 28, 37, 38, 47, 48 24 13 18, 40, 45 25 26 12 11 agnd av cc dgnd1 dgnd2 dv cc 1 dv cc 2 dgnd3 dv ee 3 n.c. clk/e clkn/e resetn/e reset/e gnd +5v (typ.) gnd +5v (typ.) +5v (typ.) (with a single power supply) gnd (with dual power supplies) gnd (with a single power supply) ?v (typ.) (with dual power supplies) ecl/ pecl pin no. symbol i i i i i/o standard voltage level equivalent circuit description dgnd3 dv ee 3 r r 1.2v r r 11 12 25 26
?5 CXA3086Q 27 clk/t clock input. 10 resetn/t ttl ttl vcc or gnd reset input. when left open, this input goes to high level. when the input is set to low level, the built-in clk frequency divider circuit can be reset. 42 inv data output polarity inversion input. when left open, this input goes to high level. (see table 1. i/o correspondence table.) power saving input. when the input is set to low level, the power saving mode is set. in this time the all ttl outputs go into the high-impedance state. normally, set to high level or left open. 41 select data output mode selection. (see table 2. operating mode table.) +4.0v (typ.) v rts +r 1 x iref 22 v rts reference voltage sense. by-pass to agnd with a 0.1f chip capacitor. 21 v rt top reference voltage. by-pass to agnd with a 1f tantal capacitor and a 0.1f chip capacitor. 16 v rb bottom reference voltage. by-pass to agnd with a 1f tantal capacitor and a 0.1f chip capacitor. v rbs ? 2 x iref +2.0v (typ.) 15 v rbs reference voltage sense. by-pass to agnd with a 0.1f chip capacitor. dv cc 1 dgnd1 1.5v r/2 r dv ee 3 10 27 dv cc 1 dgnd1 dv ee 3 44 42 dv cc 1 dgnd1 dv ee 3 41 r 1 comparator 63 r r 2 r r r comparator 62 comparator 2 r r r r comparator 1 22 21 16 15 i i i 44 ps o i i o pin no. symbol i/o standard voltage level equivalent circuit description i
?6 CXA3086Q clock output. (see table 2. operating mode table.) 30 to 35 p1d0 to p1d5 port 1 side data output. 2 to 7 p2d0 to p2d5 43 clkout port 2 side data output. 19 v in v rt to v rb i ttl o o o analog input. av cc comparator vref agnd dv ee 3 av cc 19 dv cc2 dgnd2 dv cc 1 dgnd1 100k d vee 3 43 to to 2 7 35 30 pin no. symbol i/o standard voltage level equivalent circuit description
?7 CXA3086Q resolution dc characteristics integral linearity error differential linearity error analog input analog input capacitance analog input resistance analog input current reference input reference resistance reference current residual resistance r 1 r 2 digital input (ecl, pecl) digital input voltage: high : low threshold voltage digital input current : high : low digital input capacitance digital input (ttl) digital input voltage: high : low threshold voltage digital input current : high : low digital input capacitance digital output (ttl) digital output voltage : high : low leak current during output off switching characteristics maximum conversion rate aperture jitter sampling delay clock high pulse width clock low pulse width reset signal setup time reset signal hold time clkout output delay data output delay output rise time output fall time electrical characteristics (dv cc 1, 2, av cc , dgnd3 = +5v, dgnd1, 2, agnd, dv ee 3 = 0v, v rt = 4v, v rb = 2v, ta = 25?) item symbol min. typ. max. unit conditions e il e dl c in r in i in rref * 3 iref * 4 r 1 r 2 v ih v il v th i ih i il v ih v il v th i ih i il v oh v ol i oz fc taj tds tpw1 tpw0 t_rs t_rh td_clk tdo1 tdo2 tr tf 16 0 160 6.5 3.0 3.0 dgnd3 ?1.05 dgnd3 ?3.2 ?0 ?5 2.0 ?0 ?00 2.4 ?5 140 3 2.9 2.9 3.5 0 4.5 t * 5 6.5 6 7 225 9.0 4.2 4.2 dgnd3 ?1.2 1.5 10 4.5 7 t + 1 8 2 2 0.2 0.2 150 125 308 12.5 5.7 5.7 dgnd3 ?0.5 dgnd3 ?1.4 +50 0 5 0.8 0 0 5 0.5 70 6 8 t + 2 10 bits lsb lsb pf k ? ma v v v ? ? pf v v v ? ? pf v v ? msps ps ns ns ns ns ns ns ns ns ns ns v in = 2vp-p, fc = 5msps v in = +3.0v + 0.07vrms v ih = dgnd3 ?0.8v v il = dgnd3 ?1.6v v ih = 3.5v v il = 0.2v i oh = ?ma i ol = 1ma power saving mode dmux mode clk clk resetn ?clk resetn ?clk (c l = 5pf) dmux mode (c l = 5pf) (c l = 5pf) 0.8 to 2.0v (c l = 5pf) 0.8 to 2.0v (c l = 5pf) * these characteristics are for pecl input, unless otherwise specified.
?8 CXA3086Q table 1. i/o correspondence table item symbol min. typ. max. unit conditions * 3 rref: resistance value between v rt and v rb * 4 iref = * 5 t = * 6 tps: times per sample * 7 pd = (i cc + i ee ) ?v cc + (v rt ?v rb ) 2 rref dynamic characteristics input bandwidth s/n ratio error rate power supply supply current supply current power consumption supply current power consumption i cc i ee pd * 7 i cc + i ee pd 200 54.0 0.4 290 2.0 28 37.0 34.5 67.5 0.6 360 10 ?2 10 ? 10 ? 90 0.8 470 8.0 58 mhz db db tps * 6 tps tsp ma ma mw ma mw v in = 2vp-p, ?db fc = 140msps, fin = 1khz fs dmux mode fc = 140msps, fin = 34.999mhz fs dmux mode fc = 140msps, fin = 1khz fs dmux mode error > 4lsb fc = 140msps, fin = 34.999mhz fs dmux mode error > 4lsb fc = 100msps, fin = 24.999mhz fs straight mode error > 4lsb power saving mode power saving mode { { { { { 1 fc v rt ?v rb rref 1lsb r 2 iref v rts v rt v rbs v rb 63 62 61 60 59 58 1 0 3 2 5 4 step v in r 1 iref inv 1 d5 d0 d5 d0 0 v in v rts v rbs 63 62 : 32 31 : 1 0 1 1 1 1 1 1 1 1 1 1 1 0 : 1 0 0 0 0 0 0 1 1 1 1 1 : 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 : 0 1 1 1 1 1 1 0 0 0 0 0 : 1 1 1 1 1 0 1 1 1 1 1 1 step
?9 CXA3086Q electrical characteristics measurement circuit current consumption measurement circuit v rt v in v rb av cc dv cc 1 dv cc 2 dgnd3 dgnd2 dgnd1 agnd clk/e dv ee 3 a a 5mhz pecl 4v 1.95v 2v 5v 5v icc i ee integral linearity error measurement circuit differential linearity error measurement circuit CXA3086Q a < b a > b comparator a6 to a1 a0 b6 to b1 b0 buffer controller dvm 6 6 ? ? 00? to 11? v in +v ? s2 s1 s1: on when a < b s2: on when a > b sampling delay measurement circuit aperture jitter measurement circuit CXA3086Q osc1 f : variable osc2 logic analizer 100mhz 100mhz amp ecl buffer clk v in 6 fr 1024 samples aperture jitter measurement method v in s (lsb) clk v in clk du d t v rt v rb 33 32 31 30 29 sampling timing fluctuation (= aperture jitter) error rate measurement circuit comparator a > b pulse counter CXA3086Q signal source latch latch 1/8 + signal source ?1khz f c 4 2vp-p sin wave f c v in clk clk 6 4lsb a b where s (lsb) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter taj is: taj = s / = s / ( ) ? t ? u 2 64 2 p f
?10 CXA3086Q description of operating modes the CXA3086Q has two types of operating modes which are selected with pin 41 (select). 1. dmux mode (see application circuits (1), (2) and (3).) set the select pin to vcc for this mode. in this mode, the clock frequency is divided by 2 in the ic, and the data is output after being demultiplexed by this 1/2 frequency divided clock. the 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the clkout pin. when resetting this 1/2 frequency divided clock, the low level of the reset signal should be input to the resetn pin (pin 10 or 12). the reset signal requires the setup time (t_rs 3 3.5ns) and hold time (t_rh 3 0ns) to the clock rising edge because it is synchronized with and taken in the clock. therefore, set the reset signal to low for t_rs (min.) + t_rh (min.) = 3.5ns or longer to the clock rising edge. the reset period can be extended by making the low level period of the reset signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. if the reset start timing is regarded as not important, the timing where the reset signal is set from high to low is not so consequence. however, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. in this case, the setup time (t_rs) is also necessary. see the timing chart for detail. (this chart shows the example of reset for 2t.) the a/d converter can operate at fc (min.) = 140msps in this mode. table 2. operating mode table select v cc gnd dmux mode straight mode 140msps 100msps demultiplexed output 70mbps straight output 100mbps the input clock is 1/2 frequency divided and output. 70mhz the input clock is inverted and output. 100mhz operating mode maximum conversion rate data output clock output
?11 CXA3086Q 6bit clkout data 6bit clkout data clk a b clk aaaa a aa a aaaa aaaa aaaa CXA3086Q CXA3086Q clk resetn clk resetn a b aaa a a a aaa aaa a a a aaa 6bit clkout data 6bit clkout data clk CXA3086Q CXA3086Q a b clk resetn clk resetn clk reset signal reset signal (reset period) (reset period) 2. straight mode (see application circuits (4), (5) and (6).) set the select pin to gnd for this mode. in this mode, data output can be obtained in accordance with the clock frequency applied to the a/d converter for applications which use the clock applied to the a/d converter as the system clock. the a/d converter can operate at fc (min.) = 100msps in this mode. digital input level and supply voltage settings the logic input level for the CXA3086Q supports ecl, pecl and ttl levels. the power supplies (dv ee 3, dgnd3) for the logic input block must be set to match the logic input (clk and reset signals) level. digital input level ecl pecl ttl ?v 0v 0v 0v +5v +5v ?v +5v +5v (1) (4) (2) (5) (3) (6) dv ee 3 dgnd3 supply voltage application circuits table 3. logic input level and power supply settings when the reset signal is not used. when the reset signal is used.
?12 CXA3086Q application circuit 1 (1) dmux ecl input p2d0 to p2d5 6 bit digital data p1d0 to p1d5 6 bit digital data +5v (d) dg dg 2v +5v (d) dg 6 bit digital data 6 bit digital data ecl reset signal ecl-clk dg +5v (d) ag dg latch +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag ?v (d) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 4v (2) dmux pecl input p2d0 to p2d5 6 bit digital data p1d0 to p1d5 6 bit digital data +5v (d) dg 2v +5v (d) dg 6 bit digital data 6 bit digital data pecl reset signal pecl-clk dg +5v (d) dg ag dg latch +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag +5v (d) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 4v (3) dmux ttl input p2d0 to p2d5 6 bit digital data p1d0 to p1d5 6 bit digital data +5v (d) dg 2v +5v (d) dg 6 bit digital data 6 bit digital data ttl reset signal ttl-clk dg +5v (d) dg ag dg latch +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag +5v (d) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 4v
?13 CXA3086Q (4) straight ecl input p1d0 to p1d5 6 bit digital data +5v (d) dg dg 2v +5v (d) dg 6 bit digital data ecl-clk dg +5v (d) ag dg +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 dg ecl ttl ?v (d) 4v (5) straight pecl input p1d0 to p1d5 6 bit digital data +5v (d) dg 2v +5v (d) dg 6 bit digital data pecl-clk dg +5v (d) dg ag dg +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag +5v (d) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 dg pecl ttl 4v (6) straight ttl input p1d0 to p1d5 6 bit digital data +5v (d) dg 2v +5v (d) dg 6 bit digital data ttl-clk dg +5v (d) dg ag dg +5v (d) dg +5v (d) latch dg ag ag +5v (a) ag +5v (a) ag +5v (d) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 dg 4v
?14 CXA3086Q application circuit 2 straight mode ttl i/o (when a single power supply is used) p2d5 p2d4 p2d3 p2d2 p2d1 p2d0 (msb) (lsb) 10f p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 (lsb) (msb) clk/e dv cc 2 clk/t dgnd2 p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 dgnd2 clkn/e dv ee 3 v rb v rbs av cc n.c. v in av cc v rt v rts agnd dgnd3 agnd dv cc 2 n.c. dgnd1 inv clkout ps n.c. dgnd1 dv cc 1 dv cc 2 dv cc 1 select 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 36 35 34 31 32 33 40 39 38 37 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 resetn/e dv cc 2 resetn/t p2d5 p2d4 p2d3 p2d2 p2d1 p2d0 dgnd2 reset/e dgnd2 dg +5v (d) dg ttl clk short 1f 1f 4v ag ag ag +5v (a) analog input 10f ag ag 2v short short the analog system and digital system at one point immediately under the a/d converter. see the notes on operation. clkout is the chip capacitor of 0.1f. v rbs v rts application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?15 CXA3086Q dmux mode timing chart (select = v cc ) clk v in t tpw0 tpw1 tdo2; n + 3 n + 4 n + 2 n + 5 n + 6 tds n + 1 n + 7 n 8ns (typ.) n ?1 4.5ns (typ.) td_clk; ? t p2d0 to d5 n 2.0v 0.8v 2.0v 0.8v p1d0 to d5 n + 1 n + 3 n + 2 7ns (typ.) clk out t_rs t_rh t_rs t_rh tdo1 t + 1ns (typ.) aa aa 2.0v aa 0.8v aa aa 2.0v aa 0.8v aa aa 2.0v aa 0.8v 8ns (max.) td_clk 4.5ns (min.) 8ns (max.) 4.5ns (min.) 6.5ns (min.) 10ns (max.) (reset period) reset signal ? t
?16 CXA3086Q straight mode timing chart (select = gnd) tds t tpw1 n + 1 n ?1 n n + 2 n + 3 clk v in tpw0 4.5ns (typ.) n ?3 n ?1 p2d0 to d5 p1d0 to d5 n n ?2 n ?4 n ?4 n ?2 n ?1 n ?3 n ?5 2.0v 0.8v 2.0v 0.8v clk out (clk is inverted and output.) reset signal 2.0v 0.8v td_clk; 7ns (typ.) tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 4.5ns (min.) 8ns (max.)
?17 CXA3086Q timing of a/d converter and peripheral circuit in the maximum clock rate of the demux mode, the timing of 3 channels of adc clk out in same phase is described in detail as below. for example, the clk out from one of the adc is used as the data latch clock. the clock delay and data delay are showed in the following specification, i.e. td_clk 4.5ns (min.) to 8.0ns (max.) tdo2 6.5ns (min.) to 10ns (max.) these values are considered in all the temperature change and power supply variation. when the maximum clock rate 140msps is used, the set-up time (ts) is seemed to be very small from above specifications. but the 3 channels of adc are in the same circuit board, so that the data out delay and clk out delay will be changed in same trend at the same condition of the temperature change and power supply variation. as a result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. also, 0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. these delay can be omitted in this case. when ta = 25?, v cc = +5v, the clock delay and data delay are td_clk 5.0ns (min.) to 7.5ns (max.) tdo2 7.0ns (min.) to 9.5ns (max.) the timing of the data out and clk out with above delay variation is showed in below. consequently, the set-up time for the data latching can be obtained as ts (min.) = 2.5ns. the output delay change of the data out and clk out due to the temperature change and the power supply variation should have the same trend of the delay change, the minimum ts = 2.5ns can be guaranteed at any temperature change and power supply variation. analog input r analog input g analog input b clk reset 6bit 6bit 6bit 6bit 6bit 6bit p1d/out p2d/out clk out vin clk reset CXA3086Q p1d/out p2d/out clk out vin clk reset CXA3086Q p1d/out p2d/out clk out vin clk reset CXA3086Q gate array latch clk 7ns ( = 1/140msps) th-reset reset signal td_clk (min.) 5.0ns <4.5ns> td_clk (max.) 7.5ns <8.0ns> clk out tdo2 (min.) 9.5ns <10ns> 7.0ns <6.5ns> th (min.) 6.5ns p1d/out p2d/out 14ns tdo2 (min.) ts (min.) 2.5ns note: in the timing chart, the values in the brackets < > are included all the temperature change and the power supply variation.
?18 CXA3086Q notes on operation the CXA3086Q is a high-speed a/d converter which is capable of ttl, ecl and pecl level clock input. characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. the power supply and grounding have a profound influence on converter performance. the power supply and grounding method are particularly important during high-speed operation. general points for caution are as follows. the ground pattern should be as large as possible. it is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. to prevent interference between agnd and dgnd and between avcc and dvcc, make sure the respective patterns are separated. to prevent a dc offset in the power supply pattern, connect the avcc and dvcc lines at one point each via a ferrite-bead filter shorting the agnd and dgnd patterns in one place immediately under the a/d converter improves a/d converter performance. ground the power supply pins (avcc, dvcc1, dvcc2, dv ee 3) as close to each pin as possible with a 0.1f or larger ceramic chip capacitor. (connect the avcc pin to the agnd pattern and the dvcc1, dvcc2 and dv ee 3 pins to the dgnd pattern.) the digital output wiring should be as short as possible. if the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. the analog input pin v in has an input capacitance of approximately 7pf. to drive the a/d converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. the v rt and v rb pins must have adequate by-pass to protect them from high-frequency noise. by-pass them to agnd with an approximately 1f tantal capacitor and 0.1f chip capacitor as short as possible. the offset for residual resistance is generated each for the reference voltage pins vrt and vrb. when the offset voltage has no influence on the ic operation, the voltage should be applied to the vrt and vrb pins directly, keeping the vrbs pin open. when the reference voltage is to be supplied to these pins precisely, form the feedback loop circuit with vrt and vrb as a force pin and adjust the offset voltage to be 0v. see the ?pplication circuit 2?for details. if the clkn/e pin is not used, by-pass this pin to dgnd with an approximately 0.1f capacitor. at this time, approximately dgnd3 ?1.2v voltage is generated. however, this is not recommended for use as threshold voltage v bb as it is too weak. when the digital input level is ecl or pecl level, *** /e pins should be used and *** /t pins left open. when the digital input level is ttl, *** /t pins should be used and *** /e pins left open.
?19 CXA3086Q current consumption vs. conversion rate characteristics fc ?conversion rate [msps] current consumption [ma] analog input current vs. analog input voltage characteristics analog input voltage [v] analog input current [a] reference current vs. ambient temperature characteristics ta ?ambient temperature [?] reference current [ma] 0 50 70 60 70 80 90 140 fin = ?1khz f clk 4 dmux mode c l = 5pf 234 50 100 0 ?5 25 75 current consumption vs. ambient temperature characteristics ta ?ambient temperature [?] current consumption [ma] ?5 50 25 75 55 60 65 70 7 8 9 10 11 v rt = 4v v rb = 2v example of representative characteristics
?20 CXA3086Q snr vs. input frequency response input frequency [mhz] snr [db] error rate vs. conversion rate characteristics maximum conversion rate vs. ambient temperature characteristics ta ?ambient temperature [?] fc ?maximum conversion rate [msps] 1 30 550 35 40 30 310 140 160 200 10 ? 10 ? 10 ? 10 ? 10 ?0 ?5 140 25 75 160 180 error > 4lsb fin = ?1khz f clk 4 error rate: 10 ? tps 150 170 180 error > 4lsb fin = ?1khz f clk 4 100 fc = 140msps error rate [tps] fc ?conversion rate [msps]
?21 CXA3086Q CXA3086Q evaluation board description the CXA3086Q evaluation board is a special board designed to maximize and facilitate the evaluation performance of the CXA3086Q. after latching the CXA3086Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed d/a converter. the latched data can also be extracted externally via a 24-pin cable connector. features resolution: 6 bits maximum conversion rate: 140msps (min.) supply voltage: 5.0v dual analog input pins: dir.in: ac coupling input pin amp.in: operational amplifier input pin clock frequency division: 1/1 to 1/16 absolute maximum ratings supply voltage v cc ?.5 to +7.0 v v ee ?.0 to +0.5 v recommended operating conditions min. typ. max. supply voltage v cc +4.75 +5.0 +5.25 v gnd 0 v v ee ?.25 ?.0 ?.75 v analog input amp. in ?.75 0 +1.05 v dir. in 1.5 2.0 2.2 vp-p clock input clk. in 0.8 1.0 1.2 vp-p
?22 CXA3086Q dir in con2 agnd agnd 51 w amp in con1 agnd agnd 82 w (?) v rb . r1 vrb v rt . r2 vrt offset. r3 offset b a vrt vrb s1 v rt v rb v in agnd 130 w 270 w 1k w 390 w 0.1f clk in con3 dgnd dgnd 51 w v bb clk clkout s2 pecl/ttl counter (pecl) (pecl) 4 (ttl) 4 p2d0 to d5 p1d0 to d5 CXA3086Q (ttl) 6 (ttl) 6 (ttl) 6 (ecl) 6 ttl/ecl latch dac (ttl) 6 (ecl) 6 ttl/ecl latch dac (ttl) con8 con7 p1 side data p2 side data (ecl) ttl/ecl full scale. r4 d/a out (?.0v) full scale. r5 d/a out (?.0v) dmux straight p2 side out p1 side out con5 agnd con4 agnd 1k w v ee gnd v cc con6 sw1 select sw2 a/d inv norm ps sw3 norm inv sw4 d/a inv norm inv ps block diagram
?23 CXA3086Q pin no. con1 con2 con3 con4 con5 con6 con7 con8 amp. in dir. in clk. in p2 side out p1 side out v cc gnd v ee p2 side data p1 side data i i i o o i i i o o 0.95vp-p 2.0vp-p 1.0vp-p 0 to ?v 0 to ?v +5.0v 0v ?.0v ttl ttl 0.8a ?.6a doubles the analog input signal amplitude using the operational amplifier. the input impedance is 50 . ac coupling input. suitable for sine waves and other repeating waveforms. the input impedance is 50 . the CXA3086Q operates at the pecl level clock using the sine wave-to-pecl conversion circuit. the input impedance is 50 . allows the d/a converted waveform of the CXA3086Q port 2 side data to be observed. the output impedance is 50 . allows the d/a converted waveform of the CXA3086Q port 1 side data to be observed. the output impedance is 50 . the inside of the board is divided into analog and digital systems. the CXA3086Q port 2 side data output is latched at the frequency divided clock and then output. the CXA3086Q port 1 side data output is latched at the frequency divided clock and then output. symbol i/o standard i/o level current description pin description and i/o level board adjustments and settings 1. v rb .r1: CXA3086Q v rb voltage adjusting volume. 2. v rt .r2: CXA3086Q v rt voltage adjusting volume. 3. offset.r3: adjusting volume for matching the amp.in input and dir.in input signal ranges to the CXA3086Q input range. 4. full scale.r4: full-scale adjusting volume for the port 2 d/a output. (?v: typ.) 5. full scale.r5: full-scale adjusting volume for the port 1 d/a output. (?v: typ.) 6. s1: switching junction for the dual analog input pins. set as follows according to the input pins used. 7. s2: setting junction for the clock frequency division ratio. the operating speed after latching is determined by the frequency division ratio set here. when set to clk out, it operates according to the CXA3086Q clock output. 8. sw1 select: CXA3086Q output mode selector switch. 9. sw2 a/d inv: CXA3086Q output polarity inversion switch. 10. sw3 ps: CXA3086Q ps switch. 11. sw4 d/a inv: d/a converter output polarity inversion switch. junction symbol ab amp.in dir.in open 0.1f short 10k
?24 CXA3086Q when using the board in this condition, the input signals should be input at the amplitudes shown below. (the frequency is set as desired.) analog input signal: con1 (amp.in) clock input signal: con3 (clk.in) 0v center, 800mvp-p or less 0v center, 1.0vp-p v rb .r1 = 1.5v v rt .r2 = 3.0v offset.r3 = 2.25v full scale.r4 = ?v full scale.r5 = ?v s1 a : open, b : short s2 8 : short (1/8 frequency division) 2. when the analog signal is input from the con1 (amp.in) pin, ic2:clc404 limits the input dynamic range of the a/d converter's analog input signal. 3. when the analog input signal is a sine wave or other repeating waveform, the signal can be input from the con2 (dir.in) pin with ac coupling. in these cases, the input dynamic range is not limited, but the v rt level may be limited by ic3: njm3403a. 4. in the evaluation board of the CXA3086Q, clc404 (comlinear) is employed for ic2 to drive the analog input signal. though, clc505 (comlinear) can also be used instead of clc404, there should be a little change in the peripheral circuit in this case. notes on board operation 1. the factory settings for the CXA3086Q evaluation board are as follows.
?25 CXA3086Q CXA3086Q evaluation board timing chart approximately 6.0ns approximately 9.0ns (analog regeneration waveform) operating conditions CXA3086Q operating mode analog input s2 setting : straight mode : dir in pin input : 1/2 frequency divided clock n n + 1 n + 2 n + 3 0v 0v 2vp-p 1vp-p n ?6 n ?6 n ?4 n ?2 n ?2 n ?4 n ?4 n ?3 n ?2 n ?1 (pecl) (ttl) (ttl) (ttl) con5 p1 side out CXA3086Q p1 side data CXA3086Q clk con8 p1 side data clk con3 clk in con2 dir in con8 p1 side data data 0 to ?v
?26 CXA3086Q circuit diagram dgnd r25 130 r28 82 r26 130 r29 82 r27 130 r30 82 dv cc dgnd c18 0.1f c9 1f agnd av cc c10 1f agnd c20 0.1f c21 0.1f dv cc dgnd ic3b njm3403a 7 6 5 agnd r18 51 r17 43 s1 a b dir in con2 ic2 clc404 6 2 3 agnd ic3c njm3403a 8 10 9 c17 0.1f c8 1f agnd av cc r16 270 agnd agnd ic3a njm3403a 1 2 3 c16 0.1f c7 1f agnd av cc c14 0.1f c5 1f agnd av ee c15 0.1f c6 1f agnd av ee r12 390k r11 200k r15 270 r14 130 amp in con1 r13 82 r10 22k r9 7.5k r3 10k r1 2k r2 1k r7 510 r8 510 av cc r6 51 agnd d1 tl431cp 11 4 4 7 c27 0.1f dv cc c23 0.1f r22 1k ic4b 10h116 (pecl) 6 10 9 7 ic4a 10h116 (pecl) 2 5 4 3 ic4c 10h116 (pecl) 14 13 12 15 dgnd clk in con3 c13 0.1f r20 1k r21 390 r19 51 11 ic4d 10h116 (pecl) dgnd r24 130 r23 82 dv cc dv cc c24 0.1f av ee dv ee agnd dgnd av cc dv cc v cc gnd v ee c4 33f l1 l2 l3 l4 l5 l6 c1 33f c2 33f c3 33f 2 3 4 5 6 7 9 11 12 13 14 15 clk s1 d0 s2 d1 d2 d3 q0 q1 q2 q3 cout ic5 10h136 (pecl) con6 13 14 15 16 17 18 19 20 21 22 23 24 clk/e dv cc 2 dgnd2 p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 dgnd2 clkn/e clk/t resetn/e dv cc 2 dgnd2 p2d5 p2d4 p2d3 p2d2 p2d1 p2d0 dgnd2 reset/e resetn/t dv cc 2 ps select dv cc 1 dgnd1 n.c. n.c. dgnd1 dv cc 1 dv cc 2 ic1 CXA3086Q dv ee 3 agnd v rbs v rb av cc av cc v rt v rts agnd dgnd3 n.c. v in dgnd agnd agnd clkout inv av cc c19 0.1f dgnd dgnd 25 26 27 28 29 30 36 35 34 31 32 33 dgnd dgnd 2 3 4 5 6 7 8 9 10 11 12 1 dv cc dgnd sw4 d/a inv sw3 ps sw1 select sw2 a/d inv p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 1/16 1/8 1/4 1/2 clkn clk dainv ps select adinv p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 c26 0.1f dgnd c27 0.1f dv cc dgnd dv cc dgnd dgnd c28 0.1f c25 0.1f select adinv ps clkout 40 39 38 37 41 42 43 44 45 46 47 48
?27 CXA3086Q r51 620 c31 0.1f dgnd dgnd dgnd dv cc r31 82 r34 130 r32 82 r35 130 r33 82 r36 130 dgnd dgnd s2 1/1 1/2 1/4 1/8 1/16 clkout 13 14 15 16 17 19 20 21 22 23 24 2 3 4 8 9 10 11 12 1 d0 d1 d2 d3 q0 q1 q2 q3 d4 d5 d0n d1n d2n d3n d4n d5n q4 q5 13 14 15 16 17 18 19 2 3 4 5 6 7 8 9 11 12 1 1d 1q 2d 2q 3d 3q 4d 4q 5d 5q 6d 6q 7d 7q 8d 8q oc clk 2 4 7 y1 10 b 5 6 15 13 14 12 3 1 a1 y1 y2 y2 y3 y3 y4 y4 a2 a3 a4 r50 620 dv ee dv ee dgnd c46 0.1f r49 620 c45 0.1f dv ee dgnd r38 82 r37 82 r40 130 r39 130 c54 0.1f r5 2k r44 1k r45 270 agnd d3 tl431cp agnd av ee c55 0.1f c12 1f c56 0.1f dgnd p1 side out con5 dv ee c51 0.1f r4 2k r42 1k r43 270 agnd d2 tl431cp agnd av ee c52 0.1f c11 1f c53 0.1f dgnd p2 side out con4 dv ee 13 14 16 17 18 19 12 2 3 4 7 8 9 11 1 agnd 20 10 vref av ee nc out dgnd inv 21 22 23 24 25 26 27 28 5 6 15 agnd nc nc nc nc nc dv ee c50 0.1f dgnd r41 620 dv ee ic11 10h124 13 14 16 17 18 19 12 2 3 4 7 8 9 11 1 agnd 20 10 msb vref d2 av ee d3 nc d4 out d5 dgnd d6 inv d7 21 22 23 24 25 26 27 28 5 6 15 agnd nc nc nc nc nc dv ee d8 d9 clkn lsb nc nc clk ic12 cx20201-1 ic13 cx20201-1 ic7 74as574 ic8 100390 oe v bb clkout dainv p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 1/16 1/8 1/4 1/2 clkn clk 911 ic14 74als541 dgnd 13 14 15 16 17 18 19 2 3 4 5 6 7 8 9 11 12 1 1d 1q 2d 2q 3d 3q 4d 4q 5d 5q 6d 6q 7d 7q 8d 8q oc clk ic6 74as574 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 con8 p1 side data c43 0.1f dgnd dv cc 1 2 25 26 ic14 74als541 12 13 14 15 16 17 8 7 6 5 4 3 p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 r48 620 dv ee dv ee c44 0.1f r47 620 c47 0.1f dgnd con7 p2 side data c42 0.1f dgnd dvcc dgnd 1 2 25 26 ic15 74als541 12 13 14 15 16 17 8 7 6 5 4 3 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 agnd agnd 11 msb d2 d3 d4 d5 d6 d7 d8 d9 clkn lsb nc nc clk dv cc 2 3 4 9 1 10 3d 5d 4d 0d 1d 2d e ic9 100324 16 17 15 21 22 23 24 19 5 13 14 12 11 nq2 q2 nq1 q1 nq0 q0 nq3 q3 nq4 q4 nq5 q5 2 3 4 9 1 10 3d 5d 4d 0d 1d 2d e ic10 100324 16 17 15 21 22 23 24 19 5 13 14 12 11 nq2 q2 nq1 q1 nq0 q0 nq3 q3 nq4 q4 nq5 q5 dv cc r46 620 dv ee
?28 CXA3086Q component list no. product name function ic1 CXA3086Q 6-bit a/d converter ic2 clc404aje op-amp ic3 njm3403am op-amp ic4 mc10h116l ecl buffer ic5 mc10h136l ecl countor ic6, 7 74as574n ttl latch ic8 100390 pecl ? ttl conversion ic9, 10 100324pc ttl ? ecl conversion ic11 mc10h124l ttl ? ecl conversion ic12, 13 cxa20201a-1 10-bit d/a converter ic14, 15 74als541n ttl buffer d1 to 3 tl431cp shunt regulator sw1 to 4 ate1d-2f3-10 toggle switch s1, 2 jx-1 short pin con1 to 5 01k0315 bnc connector con6 tj-563 power supply connector con7, 8 (fap-2601-1202) flat cable connector l1 to 6 zbf503d-00 ferrite-bead filter c1 to 4 tantal capacitor 33f c5 to 12 tantal capacitor 1f c13 ceramic capacitor 0.1f all parts other than those listed above chip capacitor 0.1f no. product name function r2 rj-5w-1k 1k volume resistor r1, 4, 5 rj-5w-2k 2k volume resistor r3 rj-5w-10k 10k volume resistor r47 to 51 rgld4x621j 620 network resistor r6, 18, 19 frd-25sr (0.25w) 51 r7.8 frd-25sr (0.25w) 510 r9 frd-25sr (0.25w) 7.5k r10 frd-25sr (0.25w) 22k r11 frd-25sr (0.25w) 200k r12 frd-25sr (0.25w) 390k r13, 23, 28 to 33, 37, 38 frd-25sr (0.25w) 82 r14, 24 to 27, 34 to 36, 39, 40 frd-25sr (0.25w) 130 r15, 16, 43, 45 frd-25sr (0.25w) 270 r17 frd-25sr (0.25w) 43 r20, 22, 42, 44 frd-25sr (0.25w) 1k r21 frd-25sr (0.25w) 390 r41, 46 frd-25sr (0.25w) 620 * con7 and 8 are not mounted when boards are shipped. (manufacturer: yamaichi electronics co., ltd.) component side silk diagram
?29 CXA3086Q component side pattern diagram solder side pattern diagram
?30 CXA3086Q package outline unit: mm sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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